In semiconductor packaging technologies, various methods can be used to package a semiconductor die. For example, many of today's semiconductors are packaged using so-called flip-chip technology in which a semiconductor die is attached to an underlying substrate of the package using conductive bumps.
Furthermore, semiconductor devices are being formed that include so-called through silicon vias (TSVs), which provide an electrical connection between a front side and backside of a semiconductor die, enabling interconnection of multiple die within a single package. To form such a three-dimensional die stack using TSV technology, solder bumps are formed on a die using evaporation, electroplating or screen printing technologies. However, each of these technologies suffers from drawbacks. Furthermore, an additional flux deposition is needed before a die is stacked onto an underlying die. However, this process can create high yield losses due to misalignment, particularly given the thinness and lack of tackiness of the low-viscosity flux.